1. Field of the Invention
The present invention is related to integrated circuit (IC) design systems and more particularly to characterizing timing uncertainties in ICs.
2. Background Description
Large high performance very large scale integration (VLSI) chips like microprocessors are synchronized to an internal clock. A typical internal clock is distributed throughout the chip, triggering chip registers to synchronously capture incoming data at the register latches and launch data from register latches. Ideally, each clock edge arrives simultaneously at each register every cycle and data arrives at the register latches sufficiently in advance of the respective clock edge, that all registers latch the correct data and simultaneously. Unfortunately, various chip differences can cause timing uncertainty, i.e., a variation in edge arrival to different registers.
Such timing uncertainties can arise from data propagation variations and/or from clock arrival variations. Data propagation variations, for example, may result in a capturing latch that randomly enters metastability or latches invalid data because the data may or may not arrive at its input with sufficient set up time. Clock edge arrival variations include, for example, clock frequency fluctuations (jitter) and/or register to register clock edge arrival variations (skew). Both data path and clock edge arrival variations can arise from a number of sources including, for example, ambient chip conditions (e.g., local temperature induced circuit variations or circuit heat sensitivities), power supply noise and chip process variations. In particular, power supply noise can cause clock propagation delay variations through clock distribution buffers. Such clock propagation delay variations can cause skew variations from clock edge arrival time uncertainty at the registers. Typically, chip process variations include device length variations with different device lengths at different points on the same chip. So, a buffer at one end of a chip may be faster than another identical (by design) buffer at the opposite end of the same chip. Especially for clock distribution buffers, these process variations are another source of timing uncertainty.
Furthermore, as technology features continue to shrink, power bus or Vdd noise is becoming the dominant contributor to total timing uncertainty. High speed circuit switching may cause large, narrow current spikes with very rapid rise and fall times, i.e., large dI/dt. In particular, each of those current spikes cause substantial voltage spikes in the on-chip supply voltage, even when power supply inductance (L) is minimized. Because the voltage across the inductor is V=LdI/dt, these supply line spikes also are referred to as L dI/dt noise or, simply, dI/dt noise. Since current switching can vary from cycle to cycle, the resulting noise varies from cycle to cycle. When the Vdd noise drops the on-chip supply voltage in response to a large switching event, it slows the entire chip, including both the clock path (clock buffers, local clock blocks, clock gating logic and etc.) as well as the data path logic (combinational logic gates, inverters and etc.) and may cause the chip to fail. When the noise dissipates and the on-chip supply later recovers, or even overshoots as the supply current falls; then, the circuits (buffers, gates and etc.) in these same paths speed up, returning to their nominal performance (with the normal stage delay) or even faster when the supply rises above nominal. If the supply rises too far above nominal, devices may be stressed beyond breaking to damage the chip or, at the very least reduce chip reliability. The number of stages that can complete changes as the data path slows down or speeds up relative to the clock path. Currently, in particular, such switching noise is a significant component of total timing uncertainty, comparable to skew or jitter (which are themselves affected by switching noise) or chip process variations.
Thus, it would be useful to be able to identify dI/dt noise as it occurs and minimize how it affects circuit performance.